1. Field of the Invention
This invention relates to testing integrated circuits and more particularly to improvements in the "Cross-Check" method of testing integrated circuits, which permits observation of the output node of every logic element on an integrated circuit of arbitrary combinatorial structure.
Complete testing for every defect requires controlling the output states of these nodes such that every sub-element (transistor, resistor, interconnect wire, etc.) of each logic gate is individually tested and not masked by the action of any other sub-element. This requires not only exercising every unique combinatorial state of a combinatorial logic element, but may require applying these states in certain sequential patterns to detect certain "stuck-open" faults which would otherwise be masked by the charge stored on the output node by a previous logic state.
The integration density of electronic systems is rapidly increasing due to the continuing progress in integrated circuit manufacturing technology. However, the number of pins or I/O ports to a system is growing a great deal less rapidly. This creates a problem in testing these systems, as greater amounts of test data must be funnelled through relatively few I/O ports. Additionally, the test data must traverse a continually deeper and more convoluted logical path, creating severe problems for the provision of test methods which can detect most defects.
Detecting a defect requires determining the fault that defect will create. The logic gate must then be operated or set up such that the sub-element in which the defect is located is exposed to the output in such a manner that it alone is responsible for either the correct output signal (e.g. a transistor which drives the output) or will interfere with correct operation if defective (e.g. a shorted transistor). This is done by activating all sub-elements in series with the sub-element under test and turning off all sub-elements in parallel with the sub-element under test. No known practical solution or algorithm exists to exercise and observe a logic gate in such a manner when it is embedded in a large circuit.
Definitions of the types of faults indicating defects are helpful.
An open circuit or "stuck-open" fault is a type of integrated circuit defect in which a transistor or interconnect is open circuited. These defects are difficult to detect because stored charge at the signal nodes may create a "false correct" signal at the time the output signal is observed. Correct testing for such defects requires driving the output signal to the opposite output logic level immediately prior to applying the test pattern. This assures the gate can then drive the signal back to the appropriate level being tested. This has been done in the past by creating a sequentially organized input stimulus pattern creating such a sequential pattern is often a very difficult or impractical task in a typical circuit.
An x-level fault is a fault in which the output of a logic gate does not reach a valid "one" (VOH) or "zero" (VOL) logic level. A common defect that could cause this condition to occur would be a short circuit, either internal to the gate or with another signal. Although the signal level is uncertain, the next stage of logic would consider it to be either a "one" or a "zero" depending upon the actual switching threshold of that next stage. Proper testing for x-level faults requires direct observation of the output signal levels of every gate. These outputs must have sufficient margin to assure that any arbitrary gate being driven by that node will properly detect the signal even under worst case operating conditions.
A short circuit is a type of integrated circuit defect in which one signal line or node is shorted to another, or to power or ground. Except for shorts to power or ground, these defects are very difficult to deterministically detect. Not only must every node in the circuit be compared with every other node to see when a defect would affect operation, but errors caused by these defects must be propagated to the test terminals. Rigorous determination of these conditions for large circuits has been considered impractical with even the largest computing resources. Additionally, some of these shorts may cause x-level or delay faults which are not readily determinable or detectable.
Noise margin is a measure of the degree to which an output signal exceeds the minimum electrical requirements for that signal to be considered a valid "one" or "zero" by the input port(s) of the logic gate(s) it is driving.
Output noise margin faults are similar to x-level faults in that an output node will not reach the maximum possible "one" or "zero" logic level. Instead it reaches a "one" or "zero" logic that, while valid, is insufficient to guarantee correct circuit operation in the presence of extraneous electrical noise such as that caused by other unrelated circuit switching.
Input noise margin faults are faults in which the input, while able to properly detect a valid logic signal level of value VOH or VOL, is unable to reliably detect such a signal in the presence of electrical noise. Valid input logic levels which are equal to VOH (VOL) reduced by noise are commonly referred to as VIH (minimum input logic level "one") and VIL (maximum input logic level "zero").
A delay fault is a defect causing the propagation delay of a gate or signal path to be extended sufficiently to cause incorrect operation under all or certain operating conditions. Delay faults are commonly caused by transistor defects such as transistor gates being open circuited and the transistor "stuck-on".
Stuck-at faults are defect models used to simplify characterizing the quality of the test patterns. This model assumes all defects will look like a short circuit to power or ground. This simple model is commonly used because more accurate models are impractical to use with limited computing resources. However, it does not represent an accurate model of manufacturing defects.
2. Description of Prior Art
A number of techniques have evolved which address the problems of testing large integrated circuits, notably Scan and BIST. Refer, for example, to "Built-in Self-Test Structures"; and "Built-in Self-Test Techniques" by Edward J. McCluskey, Stanford University, April 1985, IEEE Design & Test, pp 21-36; "Design for Testability - A Survey" by T.W. Williams and K. P. Parker, Proc. IEEE, Vol. 71, pp 98-112, Jan. 1983. These references describe and survey the use and applicability of these test methods.
These known techniques are severely strained at current state-of-the art manufacturing integration levels. They do not provide adequate testing, either in quantity or quality, for many possible manufacturing defects. Refer, for example, to "Test Length in a Self-Testing Environment" by T. W. Williams, pp 59-63, IEEE Design & Test; and "Fault Coverage Requirement in Production Testing of LSI Circuits" by V.D. Agrawal et. al., pp 57-61, IEEE Journal of Solid-State Circuits. Vol. SC-17, No. 1, Feb. 1982. These references describe the increasing necessity for improved fault coverage to simply maintain the same level of quality of shipped parts as the size of integrated circuits increases, and independently, as the manufacturing yield decreases.
Most presently available methods of testing are not capable of providing definitive coverage of all defects, and they are suited to testing for certain defects only with great difficulty. For example, open MOS device defects may respond correctly to certain test patterns but not to others. Avoiding these false good measurements have in the past required the input of certain sequential patterns. For instance, two-pattern tests may be necessary even for simple gates. The first pattern sensitizes the output to an initial state and the other drives it to the opposite state for checking. Such patterns are described by Gopal Gupta and N.K. Jha in "A Universal Test Set for CMOS Circuits", IEEE Transactions on Computer-Aided Design, pp 590- 597, Vol. 7, No. 5, May 1988. Creation and generation of sequential test patterns at signal inputs is very difficult and time consuming and also requires expensive computing power.
R. Rajsuman et al. describe a path sensitization scheme in "Testing of Complex Gates", Electronics Letters. July 30, 1987, Vol. 23, pp. 813-814. However, there is no suggestion therein of how to use path sensitization to derive test sets or other features and advantages of the present invention relating to test sensitization.
Dr. Tushar R. Gheewala has proposed a technique referred to as the "Cross-Check" method for testing integrated circuits which provides a higher level of test coverage. Information about this technique and products supporting this test method are available from Cross-Check Technology of San Jose, Calif. A description of features of the Cross-Check technology is found in U.S. Pat. No. 4,749,947 issued 6/7/88. This patent describes the Cross-Check technique, illustrating how, with the addition of extra apparatus and methods, the Cross-Check technique can be extended to test for all common defects.
The Cross-Check technique requires that a circuit structure be incorporated in an integrated circuit which cooperates with a software methodology. The combination provides enhanced testability by producing a very high level of observability of internal nodes of an integrated circuit. What is needed are enhancements to the Cross-Check technique to identify circuit defects which are difficult to detect by exercising input nodes and merely observing output nodes.